Nanoelectronic devices are generally fabricated on semiconductor substrates as integrated circuits. A complementary metal-oxide-semiconductor (CMOS) field effect transistor is one of the core elements of the integrated circuits. Dimensions and operating voltages of CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits.
One of the problems due to the scaling down of CMOS transistors is that the power consumption keeps increasing. This is partly because leakage currents are increasing (e.g., due to short channel effects) and because it becomes difficult to decrease the supply voltage. The latter is mainly due to the fact that the subthreshold swing is limited to minimally about 60 mV/decade, such that switching the transistor from ON to OFF needs a certain voltage variation and therefore a minimum supply voltage.
Tunnel field-effect transistors (TFETs) are typically advertised as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), because of their absence of short-channel effects and because of their resulting low off-currents. Another advantage of TFETs is that the subthreshold swing can be less than 60 mV/dec, the physical limit of conventional MOSFETs, such that potentially lower supply voltages can be used. However, all-silicon TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier.
In the past there have been different attempts to improve TFET performance.
For example Jhaveri et al. propose in “Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor”, IEEE Transactions on Electronic Devices Vol. 58, 1 (January 2011), a source-pocket TFET in order to improve the ON-current and the sub-threshold slope. For an nTFET an n+ pocket is implanted under the gate (the gate which is present above the intrinsic channel region only) in the p+-type source. As such a tunnel junction is formed between the p+ region and a narrow fully depleted pocket n+ region under the gate. Together, the p+ region and the n+ pocket region supply electrons to the channel. The fully depleted n+ pocket layer reduces the tunneling width and increases the electric field. This reduces the potential drop across the tunneling junction, thereby improving device performance.
Another possible TFET configuration is published by Vandenberghe et al. in “Analytical model for a tunnel field-effect transistor,” published IEEE Mediterranean, Electrotechnical Conference 2008, MELECON 2008. They propose a new TFET configuration wherein the gate is located fully on top of the source. The gate does not cover the channel region of the TFET device. As such Band-To-Band Tunneling (BTBT) occurs in a direction orthogonal to the gate, referred to as line tunneling, whereas in conventional TFETs BTBT tunneling occurs via the channel region, also referred to as point tunneling.
There is still a need for further improved TFET design.